Design for Testability
BTECH
4th year
EC3EV01
Digital circuit fault models, test generation algorithms, scan-based testing, Built-In Self-Test (BIST), IEEE 1149.1 boundary scan, and test compression.
Digital circuit fault models, test generation algorithms, scan-based testing, Built-In Self-Test (BIST), IEEE 1149.1 boundary scan, and test compression.